The invention relates to an interface for a data node of a data network, a data node provided with such an interface, and a data network comprising such data nodes. The data nodes of such a data network communicate with each other via a bus line interconnecting them, with each data node being capable of constituting a transmitter or a receiver.
Networks have been used for some time in motor vehicles, where they are known under the term CAN (Car Area Network). Such CAN systems comprise two open or ring-line-like shared lines, namely a bus line for data and message communication and a voltage supply line for supplying a battery voltage to the individual nodes.
The individual data nodes usually comprise a data processing unit, in particular in the form of a microcontroller, and a voltage supply unit, in particular in the form of a voltage controller, with both the microcontroller and the voltage controller being coupled via an interface to the bus line and the voltage supply line, respectively.
The voltage controller and in particular also the microcontroller consume both a relatively high current in the active state. In case of a data network having all of its data nodes in the active state, this had the effect of a correspondingly high consumption of electrical energy. This would lead to relatively fast discharging of the vehicle battery, when the vehicle is not used for a longer period of time. This problem conventionally is counteracted by switching the individual data nodes to a quiescent state when their activity is not required and by bringing them from this quiescent state to the active state only when their activity is required. For example, in case of a vehicle at standstill, in particular when it has an alarm system, the door contacts are cyclically examined. Usually the term xe2x80x9cwaking upxe2x80x9d is employed for this activation of data nodes.
When, in conventional CAN systems, data are sent from a data node via the bus line, all data nodes are awakened completely. In doing so, the voltage controller is activated in each data node via its interface in order to tap the operating voltage from the voltage supply line and to bring the microcontroller to the active mode of operation by feeding supply voltage thereto.
A message sent from a data node via the bus line contains an address part and a data part. The address part contains the addresses of the data nodes to be addressed with the respective message transmitted. An address may be intended for one single data node exclusively or for a predetermined choice of data nodes.
The individual data nodes are equipped with address filters by means of which they can recognize whether or not the address of the message transmitted via the bus line is an address intended for them.
Such an address selection or address filtering can be carried out, for example, by means of circuit arrangements and methods as indicated in the applicant""s own German patent applications 196 45 055.1 and 196 45 057.8. the contents of which are herewith incorporated by reference herein. In such address selection methods, either the entire address bit sequence as a whole or individual segments of predetermined length of the address bit sequence are compared to address words or address segments, respectively, which are stored in the respective data node. If one data node is to be capable of accepting various address codes, either a number of address filters corresponding to the number of addresses or address segments to be accepted is required or, in addition to the filters, masks are employed determining for the individual filter bit locations whether acceptance of an address bit location received is to take place for them only when the address bit of the corresponding address bit location is in conformity with the associated filter bit location, or whether acceptance is to take place irrespective of whether or not there is conformity of the respective address bit location considered with the associated filter bit location.
With conventional CAN systems, address filtering takes place in the microcontroller. When data are transmitted from a data node, full waking up of all data nodes takes place in order to enable the microcontroller of each data node by activation thereof to carry out address filtering and to thus determine whether or not the message on the bus line causing waking up is intended for the particular data node. Since the voltage controllers, and in particular the microcontrollers, consume relatively large amounts of electrical energy in the active state, even a mode of operation in which, when the vehicle is inoperative, the data nodes are brought to a quiescent state and are awakened to the active state only from time to time, mostly in cyclic manner, still results in relatively high consumption of energy and a correspondingly high load on the vehicle battery. When such a vehicle is parked for a longer period of time, for example in an airport car park during a longer air travel, the vehicle battery may be discharged as early as after periods of 1 to 2 weeks by such cyclic waking up or activation of all data nodes.
It is an advantage of the invention to provide a remedy in this respect and to make available, in particular for CAN systems, a method resulting in lower consumption of energy and thus a prolonged energy supplying capacity of the vehicle battery also in case of inoperative intervals of the vehicle of longer duration.
According to an embodiment of the invention, the interface of each data node is equipped with an activating address filter so that activating address filtering for an activating demand transmitted via the bus line can be carried out already in the interface. This eliminates the necessity of waking up the entire data node, in particular the microcontroller, for activating address filtering and switching the same to the energy-consuming active state.
The interfaces of the individual data nodes require considerably less electrical energy than the microcontroller. In addition thereto, the interfaces can be held in a low-power status when no data are transmitted via the bus line. When an activating demand is transmitted via the bus, the interfaces of all nodes, in this embodiment, are set into an active state rendering possible activating address filtering or activating address identification. In this status, all interfaces examine whether the address part of the message transmitted via the bus line contains an address intended for them.
Only when an interface recognizes an activating address intended for its data node does it effect activation of its data node, e.g., by activating a voltage controller belonging to this data node and thus waking up of the associated microcontroller to the active state thereof.
Waking up of the interfaces to their state in which they arc capable of performing activating address identification or filtering, is effected preferably by means of a characteristic frame start bit preluding the message frame of each message transmitted via the bus line.
Programming of the interface of a data node with respect to the address or addresses recognizable by the same can be effected by the associated microcontroller.
Due to the fact that the microcontrollers of conventional CAN systems have an address filter of their own, the correctness of the address identification carried out by the associated interface can be examined once more by the microcontroller after waking up of the same. However, with microcontrollers intended specifically for a data network with interfaces according to the invention, it is also possible to omit the address identification part since address filtering already takes place anyway in the interface arranged upstream thereof.
In a preferred embodiment, the individual interfaces are not only adapted to be awakened to their active state by the beginning of a message frame, but in addition thereto by an external wake-up signal. The latter may play a role, for example, when a data node belongs to one of the centrally lockable door locks and the door lock of this node is actuated for opening or closing this door. This has the effect that the door node belonging to this door lock is switched to the active state via the external wake-up signal and that this data node sends via the bus line a corresponding activation message to the data nodes associated with the other door locks, in order to cause opening or closing with respect to these additional door locks as well.
In a preferred embodiment, which is of inventive character irrespective of whether or not an interface of a data node is equipped with an address filter of its own, the interface comprises a bit clock recovering means through which the bit clock can be reconstructed from bit sequences received via the bus line. The interfaces of the CAN systems usually are provided with an oscillator of their own which, on the one hand for reasons of costs and on the other hand under the aspect of low energy consumption, are oscillators of relatively low frequency stability, for example RC oscillators. When retunable oscillators are employed therefor, these can be synchronized with this bit clock with the aid of the recovered bit clock.
In a particularly preferred embodiment of such a bit clock recovering means, a bit length counter is employed which receives, as counting clock, the oscillator signal of the interface oscillator and to which the bit change locations of the received bit sequence are reported. The count of the bit length counter reached during the duration of the start bit of the respective message frame is stored in a bit length memory, and the memory value thereof corresponds to the length of the start bit. After such bit length storage, the bit length counter is reset each time either when its count has reached the count stored in the bit length memory or when it receives information that an initial edge of a new bit has occurred in the bit sequence received, and it then starts to count anew. With each resetting operation, a bit change signal is issued at the output of the bit length counter, and these bit change signals represent the recovered bit clock.
Conventional microcontrollers comprise an oscillator of their own of high frequency stability, which in general is a quartz oscillator. Such oscillators not only involve energy consumption of their own but also are relatively expensive. In an embodiment of the invention which is of inventive character also irrespective of whether the interface of the respective data node is provided with an address filter of its own and/or with a bit clock recovering means, the microcontrollers of the individual data nodes have no oscillators of their own, but rather the microcontrollers arc controlled by means of a clock obtained by means of a controllable oscillator which is under the control of characteristic quantities transmitted via the bus line. To this end, it is possible to make use of the bit clock of the respective bit sequence transmitted as recovered in the associated interface or to take recourse to the frame length or frame partial lengths of message frames transmitted via the bus line or of cyclically transmitted, specific frequency synchronization frames.
In a preferred embodiment of the present invention, a frame length counter is employed to which the oscillator output signal of a controllable oscillator is fed as counting clock directly or after division thereof by means of a divider, with a counting operation of the frame length counter being triggered by the frame start bit of the respective message or oscillation synchronization frame. The count reached by the frame length counter at the frame end represents the respective frame length actual value. By a comparison means, this frame length actual value is compared to a frame length nominal value, and with the aid of the deviation of the frame length actual value from the frame length nominal value possibly resulting from this comparison, retuning of the controllable oscillator is performed.
In systems whose transmitted bit sequences may be of different frame lengths, a bit counter can be used as assistance, which starting with the respective frame start bit counts a predetermined number of bits, using for example the recovered bit clocks, with the result of the comparison between the frame length actual value and the frame length nominal value being released for returning control of the controllable oscillator at the moment of time at which the bit counter has counted a predetermined number of bits since the occurrence of the frame start bit. This predetermined bit count is equal to or smaller than the bit number of the shortest possible frame of the bit sequences transmitted via the system.
An interface according to a first aspect of the invention, namely an interface having an activating address filter of its own, is indicated in claim 1. An interface according to a second aspect of the invention, namely an interface with bit clock recovery, is defined in claim 14. An interface according to a third aspect of the invention, in which clock generation for control of the associated data processing unit, in particular the associated microcontroller, takes place on the basis of a characteristic quantity of bit sequences received via the bus line, is indicated in claim 22. Data nodes having such interfaces are indicated in claims 26, 32, 36 and data networks comprising corresponding data nodes are indicated in claims 38, 41, 42. Advantageous developments of the individual aspects of the invention are defined in dependent claims.